1. Field of the Invention
The present invention relates to an SOQ substrate where a silicon film is formed on a quartz substrate and a method for manufacturing the same.
2. Description of the Related Art
An SOQ (Silicon on Quartz) substrate having a silicon thin film formed on a quartz substrate is an SOI substrate expected to be applied to optical devices, for example, a device for manufacturing a TFT liquid crystal monitor. In recent years, this substrate has received attentions as a substrate intended for applications other than a general SOI substrate. To fabricate such an SOQ substrate, there is proposed a method of bonding substrates of different materials, a silicon substrate for forming an SOI layer and a quartz substrate as a handling substrate to form a silicon thin film on the quartz substrate.
Hitherto, a SOITEC method (SmartCut method) has been known as a method of bonding two substrates to manufacture an SOI substrate. This method bonds a silicon substrate prepared by implanting hydrogen ions into a bonding surface side to a handling substrate and performs heat treatment at approximately 500° C. or more to thermally delaminate a silicon thin film from a region implanted with hydrogen ions in the highest concentration. This method is based on a mechanism that “air bubbles” called “hydrogen blisters” generated at high density through hydrogen ion implantation are let “grow” under heating, and a silicon thin film is delaminated through the “bubble growth” (for example, Japanese Patent No. 3048201 or A. J. Auberton-Herve et al., “SMART CUT TECHNOLOGY: INDUSTRIAL STATUS of SOI WAFER PRODUCTION and NEW MATERIAL DEVELOPMENTS” (Electrochemical Society Proceedings Volume 99-3 (1999) p. 93-106).).
However, manufacturing an SOQ substrate with the above SOITEC method involves the following problems. According to the SOITEC method, a silicon substrate and a support substrate (insulator substrate) are bonded together and then, thermally delamination is executed along a hydrogen ion implanted boundary at a temperature of 500° C. or more. However, if two substrates having different thermal expansion coefficients, for example, a silicon substrate and a quartz substrate, are bonded and subjected to heat treatment at 500° C. or more, a thermal strain is caused by a thermal expansion coefficient difference between the two substrates, and delamination along a bonded surface or cracking tends to occur due to the thermal strain. Therefore, it is desirable to complete delamination of a silicon thin film with a lower-temperature process. In general, however, two substrates that are bonded together should be subjected to heat treatment at higher temperature in order to ensure a satisfactory bonded state throughout the entire bonding surfaces of the silicon substrate and the quartz substrate, and high bonding strength.
That is, in the case of bonding a silicon substrate and a quartz substrate to fabricate an SOQ substrate, there is a problem that a contradiction arises between a demand for a low-temperature process necessary to prevent delamination along the bonded surface or cracking from occurring due to the thermal strain caused by the thermal expansion coefficient difference between the two substrates and higher-temperature heat treatment necessary to ensure a satisfactory bonded state throughout the entire bonding surfaces. The SOITEC method cannot overcome this method.
Further, if thermal delamination is performed at a temperature of 500° C. or more, an SOI layer surface is made rough upon the delamination. As reported in Realize Co., UCS Semiconductor Substrate Technique Research Institute, “The Science of SOI”, Chapter 2 (2000), a difference in height of about 65 nm in terms of Peak to Valley (PV value) is involved in as small an area as 1 μm×1 μm. Conceivable examples of a method of flattening such a rough surface include mirror polishing and heat treatment at high temperatures (about 1100 to 1200° C.) with an atmospheric gas such as argon. Considering quartz grass transition temperatures of 1050 to 1090° C., the latter flattening method based on the high-temperature heat treatment is unsuitable as a method for manufacturing an SOQ substrate.
Thus, the surface is flattened by the former method (mirror polishing). The SOQ substrate would have a difference in height of 100 nm or more throughout the entire surface, which value is derived from the above surface roughness (about 65 nm in terms of PV value in a 1 μm×1 μm area). Hence, upon CMP polishing, for example, stock removal of 100 nm or more is required. However, according to such a stock removal, a subtle difference in polishing condition becomes apparent between a central portion and a peripheral portion of the substrate, making it difficult to ensure a uniform SOQ layer thickness throughout the entire surface of the SOQ substrate.
There has been known a method of promoting reorientation of silicon in a surface portion through hydrogen heat treatment to obtain a mirror-finished surface (for example, Sato et al., “Hydrogen Annealed Silicon-on-Insulator”, Appl. Phys. Lett. 65, pp. 1924-1926 (1994)), but this flattening process requires heat treatment at high temperatures of 1040° C. (under reduced pressure) to 1150° C. (under normal pressure) and thus is difficult to adapt to a manufacturing process for an SOQ substrate.